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The CDC 3000 series computers from Control Data Corporation were mid-1960s follow-ons to the CDC 1604 and CDC 924 systems. Over time, a range of machines were produced - divided into the upper-3000 series and the lower-3000 series. CDC phased out production of the 3000 series in the early 1970s. The 3000 series were the cash cows of Control Data during the 1960s; sales of these machines funded the company while the 6000 series was designed. The upper 3000 series used a 48-bit word size. The first machine to be produced was the CDC 3600; first delivered in June 1963. First deliveries of the CDC 3400 and CDC 3800 were in December 1965. These machines were designed for scientific computing applications, however were overshadowed by the 60-bit CDC 6000 series machines when the CDC 6600 was introduced in December 1964 and delivered in 1965. The lower 3000 series used a 24-bit word size. They were based on the earlier CDC 924 - a 24-bit version of the CDC 1604. The first lower 3000 to be released was the CDC 3200 (May 1964), followed by the smaller CDC 3100 (February 1965), and the CDC 3300 (December 1965). The final machine in the series, the CDC 3500, was released in March 1967 and used integrated circuits instead of discrete components. The 3300 and 3500 had optional relocation capabilities, floating point arithmetic, and ''BDP'' (Business + Data Processing) instructions. These machines were targeted towards business and commercial computing. The instruction set of the upper 3000 series was composed mostly of 24-bit instructions (packed two per word), but also contained some 48-bit instructions. The lower 3000 was based on a 24-bit subset of those available on the upper 3000 systems. It was therefore possible to write programs which would run on all 3000 systems. And as these systems were based on the prior 1604 and 924 instruction sets, some backward compatibility also existed. However the systems did diverge from each other in areas such as relocation and the BDP instructions. All 3000 series computers used magnetic-core memory. The CDC 3500 machine used the same core memory modules as used in the CDC 6000 / Cyber 70 series computers. == Architecture == The lower 3000 CPU was a 24-bit architecture: instructions were 24 bits in length, as were the two operand registers A and Q. There were four index registers of 15 bits, B0 through B3, though B0 is always zero (zero when read; writes do not affect the value). There was no status (flags or condition code) register. Up to 32,768 (24-bit) words of core memory could be directly addressed, and multiple banks could be switched in. Two or three memory bank configurations were the most common. Each instruction contained six bits of opcode, one bit specifying whether indirect addressing used, two bits of index register address and fifteen bits of address. Arithmetic was ones' complement, so there were two forms of zero: positive zero and negative zero. The A and Q register could function as a combined 48-bit register for certain arithmetic instructions. The E register had 48 bits. The 3300 CPU could execute around one million instructions per second (1 MIPS), giving it supercomputer status in 1965. Much of the basic architecture design of the 3000 series was done by Seymour Cray, then passed on to others to complete as he moved on to designing the CDC 6000 series. Several of the innovative features that made the 6600 'the first supercomputer' can be seen in prototype in the 3000 series. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「CDC 3000」の詳細全文を読む スポンサード リンク
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